DocumentCode :
3333193
Title :
ΔΣ ADCs with second-order noise-shaping enhancement
Author :
Wang, Yan ; Temes, Gabor C.
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA
fYear :
2009
fDate :
2-5 Aug. 2009
Firstpage :
345
Lastpage :
348
Abstract :
This paper proposes a new delay cell for noise-coupled delta-sigma analog-to-digital converters, which simplifies the design of noise-coupling circuits, as well as of the clock generator. Next, a second-order noise-shaping enhancement technique is introduced, and its architecture and circuit implementation discussed. To verify the proposed design methodology, a noise-coupled ADC was designed and simulated.
Keywords :
analogue-digital conversion; circuit noise; circuit simulation; delta-sigma modulation; network synthesis; DeltaSigma analog-to-digital converter; circuit simulation; noise-coupled delta-sigma ADC; noise-coupling circuit design; second-order noise-shaping enhancement; Adders; Circuit noise; Clocks; Coupling circuits; Delay; Noise generators; Noise shaping; Phase modulation; Sampling methods; Voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
ISSN :
1548-3746
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
Type :
conf
DOI :
10.1109/MWSCAS.2009.5236085
Filename :
5236085
Link To Document :
بازگشت