Title :
Possibilities and limitations of IDDQ testing in submicron CMOS
Author_Institution :
Dept. d´´Enginyeria Electronica, Univ. Politecnica de Catalunya, Barcelona, Spain
Abstract :
IDDQ testing is a well accepted testing approach based on the observation of the quiescent current consumption. Its growing industrial implementation is based on the possibility of detecting defects which scope other more traditional testing methods. However, its application costs are higher and its effectiveness in deep submicron technologies may decrease if the current trend of leakage increase is not stopped by creative innovation
Keywords :
CMOS digital integrated circuits; CMOS logic circuits; integrated circuit testing; leakage currents; logic testing; IDDQ testing; digital ICs; leakage; quiescent current consumption; submicron CMOS; CMOS process; CMOS technology; Circuit faults; Circuit testing; Costs; Histograms; Integrated circuit testing; Logic testing; Manufacturing; Technological innovation;
Conference_Titel :
Innovative Systems in Silicon, 1997. Proceedings., Second Annual IEEE International Conference on
Conference_Location :
Austin, TX
Print_ISBN :
0-7803-4276-3
DOI :
10.1109/ICISS.1997.630258
