Title :
Design of a Costas loop down converter
Author :
Roddewig, Mike ; Zekavat, Seyed A. ; Nooshabadi, Saeid
Author_Institution :
Dept. of Electr. & Comput. Eng., Michigan Technol. Univ., Houghton, MI, USA
Abstract :
This paper presents the the design of a digital down converter (DDC) using a digital Costas loop in a field programmable gate array (FPGA). To reduce the power dissipation we use the CIC filter to perform an efficient decimation, and then follow it with a finite impulse response (FIR) compensation filter that runs at a reduced sampling rate. The final results and performance measures are quantified and discussed. The BER performance of the Costas loop on both floating and fixed point implementations are identical.
Keywords :
FIR filters; comb filters; convertors; field programmable gate arrays; BER performance; CIC filter; Costas loop down converter design; field programmable gate array; finite impulse response filter; fixed point implementation; floating point implementation; Binary phase shift keying; Design engineering; Field programmable gate arrays; Filtering; Finite impulse response filter; Frequency; Low pass filters; Paper technology; Power dissipation; Sampling methods; Costas loop; Digital down converter; binary phase shift keying;
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2009.5236106
