Abstract :
N. mPc, a design tool for multi-processor systems, consists of six components which work together to produce functional register transfer level simulations of multiple processor, heterogeneous target systems. A meta assembler allows the user to specify the format, nmemonics, and associated bit patterns of target instruction sets. Instruction nmemonics are mapped into bit strings and output in a machine independent control/memory allocation graph. A generalized linking loader resolves the machine dependent aspects of assembler output graphs, links, and allocates the resulting image to physical memory according to user specified strategies. A hardware description language , ISP´, compiler is used to translate processor and interconnection element descriptions into executable code. This code, the linking loader outputs, and a description of the target system topology are linked by an Ecologist and Simulated Memory Processor into a simulation model which runs under the control of a Runtime Package. The Runtime Package consists of a Command Interpreter, Kernel, and Simulated Memory Manager. The Kernel and Command Interpreter permit interactive control and monitoring of simulations. The Simulated Memory Manager supervises the simulated memory contents, available physical memory, and mass storage to optimize the performance of the simulation. N. mPc is implemented on a PDP-11 system under the UNIX operating system and is currently undergoing system test and evaluation.
