CMOS 12 bits 50kS/s micropower SAR and dual-slope hybrid ADC

Author

Fang, Xiang ; Srinivasan, Vijay ; Wills, Jack ; Granacki, John ; LaCoss, Jeff ; Choma, John

Author_Institution

Inf. Sci. Inst., Univ. of Southern California, Los Angeles, CA, USA

fYear

2009

fDate

2-5 Aug. 2009

Firstpage

180

Lastpage

183

Abstract

In this paper a 12 bits 50 kS/s micropower hybrid ADC is proposed for biomimetic microelectronic systems using 0.18 mum CMOS process. The hybrid ADC combines SAR and dual-slope architectures to achieve 12 bits, power consumption 60 muW, and small silicon die size. This hybrid ADC shows very good figure-of-merits (FOM) on both power consumption and silicon die size compared with conventional low power SAR ADC. A fully differential GmC integrator is proposed for the dual-slope operation with low voltage discrete-time CMFB.

Keywords

CMOS integrated circuits; analogue-digital conversion; biomimetics; circuit feedback; discrete time systems; low-power electronics; mixed analogue-digital integrated circuits; silicon; system-on-chip; CMOS process; Si; biomimetic microelectronic systems; common-mode feedback circuitry; differential GmC integrator; dual-slope architecture; figure-of-merits; low voltage discrete-time CMFB; micropower hybrid ADC; mixed-signal SoC; power 60 muW; power consumption; silicon die size; size 0.18 mum; storage capacity 12 bit; Biomimetics; CMOS process; Capacitors; Energy consumption; Implants; Sampling methods; Signal resolution; Silicon; Voltage; Wireless sensor networks;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on

Conference_Location

Cancun

ISSN

1548-3746

Print_ISBN

978-1-4244-4479-3

Electronic_ISBN

1548-3746

Type

conf

DOI

10.1109/MWSCAS.2009.5236122

Filename

5236122