Optimized 8-level turbo encoder algorithm and VLSI architecture for LTE

Turbo code is a high performance channel coding which is able to closely reach the channel capacity of Shannon limit. It plays an important role to increase the performance in one of the latest standard in the mobile network technology tree, LTE. In this paper, a new architecture of Turbo code encoder based on 3GPP standard is proposed. This architecture is developed by implementing optimized 8-level parallel architecture, dual RAM in turbo code internal interleaver, recursive pair wise matching, and efficient 8-level index generator in turbo code internal interleaver. In order to ensure the functionality of the proposed algorithm and architecture, MATLAB software are used to simulate and to profile the system. The proposed architecture successfully increases the speed of encoder 16 times faster compared to conventional architecture with size smaller than 50%.