Title :
A nanowatt cascadable delay element for compact power-on-reset (POR) circuits
Author_Institution :
Electr. & Comput. Eng., Univ. of Idaho, Moscow, ID, USA
Abstract :
A cascadable power-on-reset (POR) delay element consuming nanowatt of peak power was developed to be used in very compact power-on-reset pulse generator (POR-PG) circuits. Operation principles and features of the POR delay element were presented in this paper. The delay element was designed, and fabricated in a 0.5 mum 2P3M CMOS process. It was determined from simulation as well as measurement results that the delay element works wide supply voltage ranges between 1.8 volt and 5 volt and supply voltage rise times between 100 nsec and 1 msec allowing wide dynamic range POR-PG circuits. It also has very small silicon footprint. Layout size of a single POR delay element was 35 mum x 55 mum in 0.5 mum CMOS process.
Keywords :
CMOS integrated circuits; cascade networks; delay circuits; low-power electronics; pulse generators; 2P3M CMOS process; POR circuits; POR-PG circuits; compact power-on-reset circuit; compact power-on-reset pulse generator; nanowatt cascadable reset POR delay element; size 0.5 mum; size 35 mum; size 55 mum; supply voltage; time 100 ns to 1 ms; voltage 1.8 V to 5 V; CMOS process; Capacitors; Circuits; Delay effects; Power generation; Power supplies; Pulse generation; Pulsed power supplies; Silicon; Voltage; CMOS; delay circuit; low quiescent current; power-on-reset (POR) circuit; pulse generator; start-up circuit; wake-up circuit;
Conference_Titel :
Circuits and Systems, 2009. MWSCAS '09. 52nd IEEE International Midwest Symposium on
Conference_Location :
Cancun
Print_ISBN :
978-1-4244-4479-3
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2009.5236153
