Title :
Reconfigurable acceleration of 3D image registration
Author :
Tsoi, Kuen Hung ; Rueckert, Daniel ; Ho, Chun Hok ; Luk, Wayne
Author_Institution :
Dept. of Comput., Imperial Coll. London, London
Abstract :
This paper proposes techniques for accelerating a software based image registration algorithm for 3D medical images targeting a reconfigurable hardware platform. Various methods, including dedicated fixed point arithmetic, error model based bit width analysis, architecture exploration and application-specific memory modules, are applied to address issues from the software algorithm and to maximize the performance of FPGA technology. Based on the reconfigurability of FPGA devices, the system can be extended to swap modules optimized for different parameters, and to adopt more advanced registration algorithms. We show that a single core on 412 MHz XC5VLX330T FPGA can evaluate a rigid transformation of a 3D image with 16 million voxels in 35 ms. With 30 cores on an FPGA, it is over 108 times faster than a multi-threaded implementation running on a 2.5 GHz Intel Quad-Core Xeon platform.
Keywords :
error analysis; field programmable gate arrays; fixed point arithmetic; image registration; medical image processing; multi-threading; optimisation; 3D image registration; FPGA technology; Intel Quad-Core Xeon platform; error model based bit width analysis; field programmable gate array; fixed point arithmetic; medical images targeting; multithreaded implementation; optimization; software algorithm; Acceleration; Algorithm design and analysis; Biomedical imaging; Computer architecture; Field programmable gate arrays; Fixed-point arithmetic; Hardware; Image registration; Performance analysis; Software algorithms;
Conference_Titel :
Programmable Logic, 2009. SPL. 5th Southern Conference on
Conference_Location :
Sao Carlos
Print_ISBN :
978-1-4244-3847-1
DOI :
10.1109/SPL.2009.4914908