SCBXP: An efficient hardware-based XML parsing technique

The need for efficient XML parsing becomes a key requirement in the underlying technologies of Web information and distributed systems. Even though new software-based XML parsing techniques have been studied to improve XML processing, the verboseness nature of XML does not help much to achieve substantial improvement. Hardware-based solutions can be an obvious choice to parse XML in a very efficient manner. In this paper, a novel hardware-based XML parsing technique is presented. The technique makes use of (1) a content-addressable memory that must be configured with a skeleton of the XML document being parsed, (2) multiple state machines acting on the multilevel nature of XML, and (3) dual-port memory modules. The architecture of an XML parser using this technique and its associated modules is designed, implemented, and tested on an FPGA. Our results show that a processing rate of at least two bytes of XML data on average is performed in each clock cycle.