Algorithm independent data flow mapping on a unified VLSI architecture

VLSI architectural unification at primitive hardware and interconnect structure level, is necessary, to cover the methodology of GPVLSI and SPVLSI systems synthesis. The concept of PACUBE array (Programmable Array of Array Adders) leads to this grand unification at macrocell level. The systolic and wavefront arrays have led to a major breakthrough in the design of supercomputing architectures. But the D-flow mapping on these arrays varies greatly depending on the algorithms to be executed, the majority of which are a combination of GIPOP equations. In this paper, both the unifying concept of the P-Arrays and the algorithm independent D-flow mapping on the P-Arrays is presented