Title :
Optimal test set for stuck-at faults in VLSI
Author :
Manjunath, K.S. ; Whitaker, S.
Author_Institution :
Idaho Univ., Moscow, ID, USA
Abstract :
Minimal test sets have the property that each input test vector tests simultaneously several faults in a circuit. Existing techniques use Boolean simplification or Karnaugh maps to achieve minimization. The authors present two new methods, one of which is a simple design by inspection technique and the other is a graphical technique. The process of minimization has been simplified by adopting the unique approach of first finding all the faults that can be detected by a single test
Keywords :
VLSI; graph theory; integrated circuit testing; integrated logic circuits; logic testing; minimisation; VLSI; design by inspection; graphical technique; input test vector; minimization; optimal test set; stuck-at faults; Circuit faults; Circuit testing; Electrical fault detection; Fault detection; Inspection; Logic testing; Minimization methods; NASA; System testing; Very large scale integration;
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
DOI :
10.1109/GLSV.1991.143950
