A programmable analogue front-end ASIC for gas micro-strip detectors having a wide range of input capacitance

The FREDA ASIC is a new mixed signal ASIC for the HOT series gas micro strip detectors. These detectors have 512 channels each having different capacitance ranging from 2pF-80pF. This new ASIC is an upgrade to the previous programmable version of FREDA with new signal processing capabilities. It is a 16 channel ASIC each of which consists of a Peak Detect and De-randomiser, 8 bit counter, 12 bit hybrid SAR ADC with multiplexed LVDS outputs in addition to a preamplifier, a programmable CR-RC shaper and a programmable gain amplifier. The peak detect de-randomiser is a 3 bit analogue peak hold pipeline to store randomly arriving pulses at an average data rate of 1 MHz. It also allows baseline measurements of the shaper output during low periods to activity to enable correlated double sampling. A 100 MHz, 8 bit counter is used to generate a timestamp which is controlled by the peak detect signal. The 12 bit hybrid SAR ADC generates its 4MSBs from a resistor string and the rest 8 bits from a capacitor bank, it uses a 20 MHz clock and takes 800 ns for a single data conversion. This ASIC has been manufactured using a 0.35 m CMOS process. The ASIC architecture is described including simulated and measured results.