DocumentCode
3335511
Title
Building block layout based on block compaction and two-adjacent-side channel router
Author
Yamada, Shoichiro ; Tanabe, Hirohisa
Author_Institution
Dept. of Electr. Eng., Osaka Prefecture Univ., Japan
fYear
1991
fDate
1-2 Mar 1991
Firstpage
231
Lastpage
236
Abstract
The authors propose a new layout method based on a block compaction and two-adjacent-side channel router for building block VLSI. In this method, the block compaction and global routing are carried out simultaneously and by introducing a new channel router it is possible to avoid unnecessary detour of the wires and reduce the dead space. The present channel routing approach has a remarkable feature that its routability is 100%. Experimental results are shown to compare this method with the previous method
Keywords
VLSI; circuit layout CAD; graph theory; CAD; VLSI; block compaction; building block layout; global routing; two-adjacent-side channel router; Compaction; Educational institutions; Equations; Pins; Routing; Shape; Strontium; Very large scale integration; Wires; Wiring;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location
Kalamazoo, MI
Print_ISBN
0-8186-2170-2
Type
conf
DOI
10.1109/GLSV.1991.143971
Filename
143971
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