DocumentCode :
3335557
Title :
Test plan generation and concurrent scheduling of tests in the presence of conflicts
Author :
Wilson, T.C. ; Basu, A. ; Banerji, D.K. ; Majithia, J.C.
Author_Institution :
Dept. of Comput. & Inf. Sci., Guelph Univ., Ont., Canada
fYear :
1991
fDate :
1-2 Mar 1991
Firstpage :
243
Lastpage :
248
Abstract :
When BILBO tests are being generated and scheduled, resource conflicts between I-paths and tests present many difficulties. The authors explore: how pipelining is limited by potential internal conflicts; ways to promote pipelining during test plan generation and how to incorporate a test into a test phase already containing tests that conflict with it. They do not directly address the general problems of test plan generation or test scheduling. What is offered is insight into the difficulties that (potential) conflicts provide and techniques for handling these difficulties. The insights are primarily theoretical, but the resulting techniques could be viewed as possible extensions to existing methodologies
Keywords :
built-in self test; integrated logic circuits; logic testing; pipeline processing; scheduling; BILBO tests; BIST; concurrent scheduling; pipelining; resource conflicts; self testing; test plan generation; Delay; Information science; Logic testing; Performance evaluation; Pipeline processing; Processor scheduling; Test pattern generators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
Type :
conf
DOI :
10.1109/GLSV.1991.143973
Filename :
143973
Link To Document :
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