A poly to active region VLSI mask alignment test structure

Author

Ramesh, Tirumale

Author_Institution

Dept. of Electr. Eng., Saginaw Valley State Univ., Univ. Center, MI, USA

fYear

1991

fDate

1-2 Mar 1991

Firstpage

278

Lastpage

283

Abstract

Present day CMOS technologies require continuous evaluation of the technology in terms of optimizing the design rules. Electrical monitoring of mask alignment is one such evaluation tool. A VLSI test structure for monitoring the poly to active region mask misalignment is presented. The structure is designed based on 2-micron scalable CMOS (SCMOS) design rules. The issues related to sensitivity of the measurement, and some critical design considerations are discussed

Keywords

CMOS integrated circuits; VLSI; integrated circuit technology; integrated circuit testing; masks; monitoring; 2 micron; CMOS technologies; VLSI mask alignment; electrical monitoring; lithographic mask; poly to active region mask misalignment; test structure; CMOS technology; Contacts; Design optimization; Floors; Monitoring; Resistors; Semiconductor device measurement; Testing; Very large scale integration; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI, 1991. Proceedings., First Great Lakes Symposium on

Conference_Location

Kalamazoo, MI

Print_ISBN

0-8186-2170-2

Type

conf

DOI

10.1109/GLSV.1991.143979

Filename

143979

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=3335659