An advanced FPGA based phase-lock-loop system as an alternative solution for the XFEL timing system

The European XFEL project requires a high-speed, very precise clock and timing distribution over large distances. A prototype system which fulfils current requirements that uses high-end components has just been completed and is being tested. However, the system is quite complicated and the boards are very complex, being designed using the small micro-TCA form factor. A way to simplify the system, and perhaps reduce cost, would be to implement an Advanced PLL in the programmable logic of an FPGA, which then would control an external VCO. By doing so several major issues could be resolved at the same time, while making more use of the advanced features of modern FPGAs. Such a system could be an alternative solution to the complex part of the Timing and Triggering System for XFEL.