Title :
Sequence invariant state machine compiler
Author :
Buehler, D. ; Whitaker, S. ; Canaris, J.
Author_Institution :
Intel Corp., Hillsboro, OR, USA
Abstract :
A CAD tool for automatic generation of VLSI state machines based on a sequence invariant architecture is presented. The program, which is process independent, operates on a flow table input and produces a layout archive. Using an incremental approach for layout also allows subcircuits to be generated
Keywords :
VLSI; circuit layout CAD; logic CAD; CAD tool; VLSI state machines; automatic generation; flow table input; layout archive; sequence invariant architecture; state machine compiler; tile generation; Automatic logic units; Circuit synthesis; Latches; Logic arrays; Logic circuits; Logic design; Programmable logic arrays; Switches; System performance; Very large scale integration;
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
DOI :
10.1109/GLSV.1991.143986
