DocumentCode :
3335943
Title :
HADES-high-level architecture development and exploration system
Author :
Poechmueller, P. ; Held, M. ; Wehn, N. ; Glesner, M.
Author_Institution :
Inst. of Microelectron. Syst., Darmstadt Univ. of Technol., Germany
fYear :
1991
fDate :
1-2 Mar 1991
Firstpage :
342
Lastpage :
343
Abstract :
The authors propose a new approach to high level behavioural synthesis starting from an algorithmic description in Hardware C. The algorithm is compiled into a corresponding data/control flow graph including several optimizations. The behavioural synthesis part of the system performs transformations like loop unrolling, parallelization, etc., whereby the user is supported through a feedback loop. For final structural synthesis an advanced tool based on genetic algorithms is provided. Layout synthesis is assumed to be performed by available tools like the GENESIL silicon compiler
Keywords :
circuit CAD; circuit layout CAD; logic CAD; CAD; GENESIL; HADES; computer aided design; data/control flow graph; feedback loop; genetic algorithms; high level behavioural synthesis; high-level architecture development; layout synthesis; loop unrolling; optimizations; parallelization; silicon compiler; structural synthesis; Control system synthesis; Cost function; Feedback loop; Genetic algorithms; Hardware; High level synthesis; Microelectronics; Silicon compiler; Space exploration; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI, 1991. Proceedings., First Great Lakes Symposium on
Conference_Location :
Kalamazoo, MI
Print_ISBN :
0-8186-2170-2
Type :
conf
DOI :
10.1109/GLSV.1991.143995
Filename :
143995
Link To Document :
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