DocumentCode :
3336093
Title :
OASIS: a silicon compiler for semi-custom design
Author :
Kedem, G. ; Brglez, Franc ; Kozminski, Krzysztof
Author_Institution :
Dept. of Comput. Sci., Duke Univ., Durham, NC, USA
fYear :
1990
fDate :
4-7 Jun 1990
Firstpage :
75
Abstract :
OASIS is a cell-based silicon compiler system that supports rapid implementation of digital Application specific ICs (ASICs). The system automates the design process by taking a high-level language description and producing a layout of a testable IC. OASIS facilitates design of large digital systems on silicon and gives the designer sufficient control to enable exploration of the speed-versus-area design tradeoffs. The front end of OASIS is the LOGIC-III compiler that translates a high-level language description into a hierarchical netlist of gates. The LOGIC-III language is a PASCAL-like language that allows the designer to specify his design completely and in a uniform, consistent manner. The language supports both the logic synthesis for FSMs and combinational logic, and the structural/algorithmic synthesis of data paths and regular structures such as adders or multipliers. The OASIS system comprises an integrated set of tools for complete design, simulation, verification, layout and testing of ASICs. Experience with the system shows a marked increase in design productivity when compared with more traditional design techniques. The authors describe the system with its unique features and present some of the results of using OASIS in designing semi-custom ASICs
Keywords :
Pascal; application specific integrated circuits; circuit layout CAD; logic CAD; FSMs; LOGIC-III compiler; OASIS; PASCAL-like language; combinational logic; data paths; design productivity; digital Application specific ICs; hierarchical netlist; high-level language description; layout; semi-custom design; silicon compiler; speed-versus-area design tradeoffs; structural/algorithmic synthesis; testable IC; verification; Automatic testing; Digital integrated circuits; High level languages; High speed integrated circuits; Integrated circuit layout; Integrated circuit testing; Logic; Process design; Silicon compiler; System testing;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Rapid System Prototyping, 1990. Shortening the Path from Specification to Prototype, First International Workshop on
Conference_Location :
Research Triangle Park, NC
Print_ISBN :
0-8186-2175-3
Type :
conf
DOI :
10.1109/IWRSP.1990.144036
Filename :
144036
Link To Document :
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