Low leakage power in sub-45nm with multiple threshold voltages and multiple gate-oxide thickness footed domino circuits

A circuit technique is proposed in this paper for simultaneously reducing both subthreshold and gate-oxide leakage power consumption at high and low temperatures in footed domino logic circuits. A high V_t pMOS pull-up technique with feedback control utilizing both multiple-V_t and multiple T_ox is added between the footer node and dynamic node to place footed domino logic circuit into a low leakage state. At 110^oC, proposed work improves 34%-50% as compared to multiple-V_t with low and high inputs. At room temperatures, proposed work improves 20%-27% as compared to multiple-V_t with low and high inputs.