WTM based reordering of combine test vector & output response using Dijkstra algorithm for scan power reduction

Test power has become a serious problem with scan-based testing. It can lead to prohibitive test power in the process of test application. During the process of scan shifting, the states of the flip-flops are changing continually, which causes excessive switching activities. Test vector reordering for reducing scan in scan out power is one of the general goal of low power testing. In this paper Dijakstra algorithm is proposed to reorder the test vectors in an optimal manner to minimize switching activity during testing. Here, by passing the test vectors through output response a weighted transition matrix(WTM) is calculated, and then Dijkstra algorithm is applied which helps to reduce switching activities. The experimental results on ISCAS benchmark circuit proves that the proposed algorithm gives an average of 39.95% reduction in switching.