Efficient VLSI architecture of visual distortion sensitivity based spatially adaptive quantization for image compression

As the visual distortion sensitivity based spatially adaptive quantization (VDSSAQ) algorithm considers human visual system (HVS) and tunes the quantizer´s steps in a finer manner to improve the perceptual quality, it usually causes considerable computing complexity and memory access overhead. To address this problem, this paper presents a new and efficient very large scale integration (VLSI) architecture for the implementation of VDSSAQ. The proposed architecture exploits the parallelism between wavelet transform and quantization as well as quantization algorithm itself to speed up the computing process. Besides, a delaying quantization operation scheme is designed to work with the bitplane coder (BPC) to further reduce the time consumption and memory accesses significantly. Experimental results show that the proposed VLSI architecture outperforms the state-of-the-art architectures with the least memory accesses and highest overall throughput, which makes it desirable in real time image compression applications.