An FPGA implementation of a simple lossless data compression coprocessor

The paper describes a Field Programmable Gate Array (FPGA)-based lossless data compression coprocessor using implementing a compression method developed by Rice. We have implemented the Rice code (both encoder and decoder) for 8 bit/sample data on an FPGA Xilinx XC4005. The code has been designed to be optimal on 1.5 <; H <; 7.5 bits/sample, that is usually required in lossless image compression. The encoder and decoder can achieve 11.6 MHz and 19.4 MHz clock, respectively, where a 10 MHz clock corresponds to a 1.5 Mbits/s throughput. The XC4005 contains combinatorial logic units (CLU) and I/O pins. The Rice encoder uses 30% CLB F&G, 15% CLB H, 16% CLB FF, and 34% I/O pins. The Rice decoder uses 31% CLB F&G, 19% CLB H, 16% CLB FF, and 34% I/O pin. Hence, an X4005 is sufficient to implement both encoder and decoder.