Title :
Design of dynamic circuits with enhanced noise tolerance
Author :
Bobba, S. ; Hajj, I.N.
Author_Institution :
Coordinated Sci. Lab., Illinois Univ., Urbana, IL, USA
Abstract :
In this paper, we present a design technique that increases the noise tolerance of dynamic circuits. We present a low-noise circuit which has very low leakage and variable input noise margin. This circuit can be used in the design of noise-tolerant dynamic wide-OR gates which are otherwise extremely vulnerable to noise at the inputs and charge leakage from the dynamic evaluation node. High speed decoders and comparators used in a cache can be realized using dynamic wide-OR gates. We present simulation results to demonstrate the effectiveness of the proposed design technique compared to other techniques. We also present the application of the low-noise circuit to enhance the noise immunity of dynamic SOI gates against parasitic bipolar leakage
Keywords :
circuit simulation; comparators (circuits); high-speed integrated circuits; integrated circuit design; integrated circuit noise; leakage currents; logic CAD; logic gates; logic simulation; charge leakage; comparators; dynamic SOI gates; dynamic circuits; dynamic evaluation node; dynamic wide-OR gates; high speed decoders; low-noise circuit; noise immunity; noise tolerance; simulation results; variable input noise margin; CMOS logic circuits; Circuit noise; Clocks; Coupling circuits; Integrated circuit interconnections; Logic circuits; MOS devices; Noise figure; Parasitic capacitance; Phase noise;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806473
