DocumentCode
3338180
Title
Settling time modeling of the ground bounce produced into the switching buffer
Author
Motta, E.M.
Author_Institution
Escuela de Ciencias de la Electron., Univ. Autonoma de Puebla
fYear
1999
fDate
1999
Firstpage
59
Lastpage
63
Abstract
This paper presents a macromodel for modeling the ground bounce produced by the buffer in switching state. The timing macromodel used to implement this technique is up to several times faster than Spice2 and up to several times faster than existing nonlinear macromodels. The accuracy of this macromodel over a wide range of operating conditions is demonstrated. The macromodel can be used to minimize VLSI simulation time, and generate data for high-level macromodels
Keywords
CMOS digital integrated circuits; VLSI; circuit simulation; integrated circuit design; integrated circuit modelling; logic CAD; timing; VLSI simulation time; ground bounce; high-level macromodels; operating conditions; settling time modeling; switching buffer; switching state; timing macromodel; Circuit simulation; Equations; Inverters; Logic; Optical buffering; Timing; Transconductance; Transistors; Very large scale integration; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location
Washington, DC
Print_ISBN
0-7803-5632-2
Type
conf
DOI
10.1109/ASIC.1999.806474
Filename
806474
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