A reconfigurable digital filter chip for image processing

Author

Torres, L. ; Robert, M. ; Colancon, S. ; Paindavoine, M.

Author_Institution

Univ. des Sci. et Tech. du Languedoc, Montpellier, France

fYear

1999

fDate

1999

Firstpage

93

Lastpage

97

Abstract

The scope of this paper is to present a Programmable Digital Filter (PDF) design. This architecture can be programmed to implement any eight order Infinite Impulse Response (IIR) or Finite Impulse Response (FIR) filters. The coefficient, input and output data word lengths are coded on 16 bit, internal results are on 32 bit. A first low cost VLSI implementation of this architecture was validated and tested successfully in a 0.7 μm CMOS technology, with an area of 27 mm² and a maximum clock frequency of 40 MHz. The migration in a 0.25 μm CMOS process allows us to reach a 150 MHz clock frequency with an area of 5 mm². A specific board has been developed for fast prototyping of real time image processing applications

Keywords

CMOS digital integrated circuits; FIR filters; IIR filters; VLSI; application specific integrated circuits; digital filters; digital signal processing chips; high-speed integrated circuits; image processing equipment; programmable filters; real-time systems; 0.25 micron; 0.7 micron; 150 MHz; 16 bit; 32 bit; 40 MHz; CMOS technology; FIR filter; IIR filter; eight-order filter; image processing chip; low cost VLSI implementation; programmable digital filter design; real time image processing applications; reconfigurable digital filter chip; CMOS technology; Clocks; Costs; Digital filters; Finite impulse response filter; Frequency; IIR filters; Image processing; Testing; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-5632-2

Type

conf

DOI

10.1109/ASIC.1999.806482

Filename

806482