Architecture of embedded zerotree wavelet based real-time video coder

Author

Omaki, Roberto Yusi ; Fujita, Gen ; Onoye, Takao ; Shirakawa, I.

Author_Institution

Dept. Inf. Syst. Eng., Osaka Univ., Japan

fYear

1999

fDate

1999

Firstpage

137

Lastpage

141

Abstract

A VLSI architecture of a real-time wavelet video coder is described, with the main focus put on the efficient VLSI implementation and scalable code generation. To achieve this goal, this architecture devises a modified 2-D sub-band decomposition scheme in conjunction with a parallelized block-based EZW (Embedded Zerotree Wavelet) coding. Experimental results are also shown in comparison with MPEG2 so as to demonstrate the viability of the proposed architecture

Keywords

CMOS digital integrated circuits; VLSI; application specific integrated circuits; digital signal processing chips; discrete wavelet transforms; real-time systems; video coding; 0.35 micron; DSP chip; DWT; VLSI architecture; embedded zerotree video coder; modified 2D sub-band decomposition scheme; parallelized block-based coding; real-time video coder; scalable code generation; wavelet based video coder; Arithmetic; Bandwidth; Discrete cosine transforms; Discrete transforms; Discrete wavelet transforms; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-5632-2

Type

conf

DOI

10.1109/ASIC.1999.806491

Filename

806491