Title :
ATLAS II: optimizing a 10 Gbps single-chip ATM switch
Author :
Pnevmatikatos, Dionisios ; Kornaros, George
Author_Institution :
Inst. of Comput. Sci., Found. for Res. & Technol.-Hellas, Crete, Greece
Abstract :
We describe ATLAS II, an optimized version of the ATLAS I ATM switch. While in ATLAS I we concentrated on correctness, in ATLAS II we concentrate on optimizing the area and the performance of the switch. To achieve these goals we utilize improved design techniques and circuitry, and we eliminate functionalities of marginal benefit. Our results show that we can achieve significant performance and cost benefits, requiring only a small increment in manpower
Keywords :
CMOS digital integrated circuits; VLSI; application specific integrated circuits; asynchronous transfer mode; circuit optimisation; electronic switching systems; field effect transistor switches; high-speed integrated circuits; integrated circuit design; integrated circuit layout; switching circuits; 10 Gbit/s; ATLAS II; CMOS IC; area optimisation; cost benefits; design techniques; performance optimisation; single-chip ATM switch; Application software; Asynchronous transfer mode; CMOS technology; Circuits; Computer networks; Computer science; Cost function; High performance computing; Switches; Very large scale integration;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806492
