Title :
Two-way circuit partitioning by iterative improvement and logic perturbation
Author :
Shen, Ming-Feng ; Chen, Shao-Yuan ; Tu, Shen-Chi ; Wang, Ting-Chi
Author_Institution :
Dept. of Inf. & Comput. Eng., Chung Yuan Christian Univ., Chung Li, Taiwan
Abstract :
In this paper, we present five algorithms that simultaneously consider both the graph domain and logic domain for two-way min-cut circuit partitioning, To handle both domains, the iterative improvement and logic perturbation techniques are employed. The experimental results show that our algorithms are capable of generating better or comparable partitioning results as compared to the algorithm presented by Cheng et al. (1995)
Keywords :
circuit CAD; integrated circuit design; iterative methods; logic CAD; logic partitioning; perturbation techniques; iterative improvement; logic perturbation; min-cut circuit partitioning; two-way circuit partitioning; Algorithm design and analysis; Constraint optimization; Coupling circuits; Iterative algorithms; Iterative methods; Logic circuits; Logic functions; Partitioning algorithms; Perturbation methods; Very large scale integration;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806496
