DocumentCode :
3338624
Title :
CubicWare: a hierarchical design system for deep submicron ASIC
Author :
Jang, Myung-Soo ; Jin, Hoon-Sang ; Lee, Byoung-Hyun ; Lee, Jin-Yong ; Song, Seong-Jin ; Kim, Taek-Soo ; Kong, Jeong-Taek
Author_Institution :
CAE Team, Samsung Electron. Co. Ltd., South Korea
fYear :
1999
fDate :
1999
Firstpage :
168
Lastpage :
172
Abstract :
In this paper, we present CubicWare, a hierarchical design system which can estimate both timing and power consumption at the pre-layout stage. CubicWare consists of a floorplanner (CubicPlan), a delay calculator (CubicDelay), and a power estimator (CubicPower). CubicPlan provides accurate estimation of the interconnect parasitics, and CubicDelay calculates the delay including the effect of interconnects. Based on this delay, logic simulation is performed to verify the functionality and timing of the design. In the process, switching statistics on each gate is obtained. CubicPower reads the switching statistics and the power characteristics of gates to estimate the power consumption. The proposed parasitics estimation algorithm in CubicPlan can consider the coupling capacitances of the interconnects using the wiring congestion map. This approach provides a significantly improved correlation with the post-layout than the conventional statistical methods in terms of interconnect capacitances. CubicWare also supports the full functions of hierarchical manipulations including hierarchical delay calculation. The timing estimation of CubicWare at the pre-layout stage shows less than 10% error compared to the post-layout result. Experimental results of the dynamic power estimator at the gate level shows less than 10% error compared to the results of Powermill and the measured values of the IMS tester
Keywords :
application specific integrated circuits; circuit CAD; circuit layout CAD; delay estimation; high level synthesis; integrated circuit design; integrated circuit layout; logic simulation; timing; CubicDelay; CubicPlan; CubicPower; CubicWare; coupling capacitances; deep submicron ASIC; delay calculator; floorplanner; hierarchical design system; interconnect parasitics; logic simulation; parasitics estimation algorithm; power consumption; power estimator; pre-layout stage; switching statistics; timing; wiring congestion map; Application specific integrated circuits; Delay effects; Delay estimation; Energy consumption; Logic design; Parasitic capacitance; Power system interconnection; Statistics; Timing; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
Type :
conf
DOI :
10.1109/ASIC.1999.806497
Filename :
806497
Link To Document :
بازگشت