DocumentCode :
3338639
Title :
Utilization of carry-save-adders in arithmetic optimization
Author :
Um, Junhyung ; Kim, Tacwhan
Author_Institution :
Dept. of Comput. Sci., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea
fYear :
1999
fDate :
1999
Firstpage :
173
Lastpage :
177
Abstract :
Carry-save-adder (CSA) is one of the most widely used types of operations for implementing fast computations of arithmetics in industry. It was reported that typical arithmetic computations found in industry designs were optimized using CSAs, producing designs with on average over 20% faster timing (without any area penalty). Being stimulated by the results, we analyze and formulate the problem of allocating CSAs for an arithmetic expression, and present an effective algorithm which constructs a functionally equivalent CSA tree with a minimal timing. Specifically, we solve the CSA allocation problem in two steps: (1) allocating a delay-optimal CSA tree for the multi-bit inputs of the arithmetic expression and (2) determining the assignment of the single-bit inputs to carry inputs of CSAs which leads to a minimal increase of delay of the CSA tree obtained in step (1). For a number of arithmetic expressions found in real designs, it was demonstrated that our approach is very effective and produces designs with up to 54% faster timing and up to 42% smaller area
Keywords :
adders; carry logic; delays; logic design; optimisation; timing; CSA allocation problem; arithmetic optimization; carry-save-adders; delay-optimal CSA tree; functionally equivalent CSA tree; minimal timing; multi-bit inputs; single-bit inputs; Arithmetic;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
Type :
conf
DOI :
10.1109/ASIC.1999.806498
Filename :
806498
Link To Document :
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