Test ready core design for a DSP core

In this paper, test ready core design techniques for SSP1820, a hard core compatible with the OakDSPCore, are presented. The basic strategy is to implement a serial test access structure with test isolation capability around the hard core so that the pre-developed functional test vectors can be applied serially. To provide multiple integration choices, two serial test access schemes of JTAG and isolation rings with different number of scan chains are considered. Compared to the original core, the test ready cores implemented offer the advantage of test access and test isolation with less pin overhead. Especially, several integration choices available for the core can enable efficient core test integration to meet various design-specific test requirements