The impact of Cu/low κ on chip performance

Author

Zarkesh-Ha, Payman ; Bendix, Peter ; Loh, William ; Lee, JinJoo ; Meindl, James D.

Author_Institution

Microelectron. Res. Center, Georgia Inst. of Technol., Atlanta, GA, USA

fYear

1999

fDate

1999

Firstpage

257

Lastpage

261

Abstract

A new model to predict percentage of performance improvement using copper and/or low κ is rigorously derived. Based on the new model, it is shown that for a typical ASIC design in 0.25 μm technology, using copper interconnect alone can improve the speed by about 10%; however in the same technology, using low κ dielectric (ε_r=2.5) alone can improve the speed by about 27%. The new model indicates that the performance gain for copper and low κ are not additive. Finally, the model is applied to the NTRS projections to explore the performance gain through future technology generations

Keywords

CMOS integrated circuits; application specific integrated circuits; copper; dielectric thin films; integrated circuit interconnections; integrated circuit modelling; 0.25 micron; ASIC design; Cu; Cu interconnect; chip performance; low κ dielectric; performance improvement; Aluminum; Artificial intelligence; Clocks; Computational modeling; Copper; Delay; Large scale integration; Microelectronics; Performance gain; Power system modeling;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-5632-2

Type

conf

DOI

10.1109/ASIC.1999.806515

Filename

806515