Title :
Power analysis of gated pipeline registers
Author :
Ye, Wu ; Irwin, Mary Jane
Author_Institution :
Dept. of Comput. Sci. & Eng., Pennsylvania State Univ., University Park, PA, USA
Abstract :
System-on-chip (SoC) is becoming a reality as industry begin to combine a wide range of complex functionalities on a single die. System power optimization becomes an important issue in ensuring practical packaging and system reliability. In this paper, we measure the benefits of using clock gating on pipeline registers in a RISC datapath. Different pipeline register fields are gated by different already available control signals. The architectural level simulation results show that this technique can effectively reduce switch capacitance by 55.2% for pipeline registers and 22.1% for the datapath on average
Keywords :
circuit optimisation; clocks; flip-flops; integrated circuit design; logic simulation; low-power electronics; pipeline processing; reduced instruction set computing; shift registers; D flip-flop; RISC datapath; architectural level simulation; clock gating; gated pipeline registers; packaging; pipeline register fields; power analysis; switch capacitance reduction; system power optimization; system reliability; system-on-chip; Capacitance; Circuit simulation; Clocks; Flip-flops; Pipelines; Power engineering computing; Registers; Reliability engineering; Switches; Switching circuits;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806520
