Power analysis of gated pipeline registers

System-on-chip (SoC) is becoming a reality as industry begin to combine a wide range of complex functionalities on a single die. System power optimization becomes an important issue in ensuring practical packaging and system reliability. In this paper, we measure the benefits of using clock gating on pipeline registers in a RISC datapath. Different pipeline register fields are gated by different already available control signals. The architectural level simulation results show that this technique can effectively reduce switch capacitance by 55.2% for pipeline registers and 22.1% for the datapath on average