Scaling and design of a 16-mega-pixel CMOS image sensor for electron microscopy

The design and scaling of a 21 mm × 21 mm CMOS image sensor for charged-particle imaging, ¿EM7,¿ is presented and compared to its smaller prototype, EM5. The sensor contains ~50 million transistors spanning its 16 million pixels, and includes over 4,100 parallel analog processing and A/D conversion circuits, utilizing 12 parallel 10-bit readout busses for high data throughput. The clock distribution design in EM7 minimizes the clock delay by dividing the chip into multiple parallel sections, each driven locally by a tree-like clock structure. By this technique, simulations showed that the readout shift-register clock delay is reduced from 4.7 ns to 0.14 ns, and the row shift-register clock delay is reduced from 1.7 ns to 0.12 ns. With similar local buffering, the ADC gray code counter delay is reduced from 35 ns to 0.9 ns. These improvements allow EM7 to sustain image acquisition at 75 frames/s, for a continuous data throughput of over 10 Gb/s. The large chip dimensions and the increased power consumption in EM7 also require more robust power distribution. A matrix-math simulation shows the worst-case pixel IR voltage drop was improved from 20 mV to 8 mV. Similarly, the pixel´s worst-case analog output´s IR drop is reduced from 80.7 mV to 2.58 mV, and its bandwidth is thus increased from 6.92 MHz to 14.4 MHz. The power supply IR drop in the output processing stage´s op-amps is reduced from 327 mV to 35 mV, their open-loop gain variation is reduced from 525% to 28%, and their worst-case bandwidth is increased from 0.87 MHz to 764 MHz.