Block-level thermal model for floorplan stage in VLSI design flow

Thermal issues have become a determinant factor to result in very large scale integrated (VLSI) circuits work or malfunction. For this reason, the paper proposed an efficient block-level thermal model for temperature calculation in the floorplan stage among the integrated circuit (IC) design flow. Furthermore, the model accurately profiles the temperature difference between all thermal blocks and overcomes the very long computational time issue existing in traditional tile-based thermal model. We not only prove the timing complexity by theory but also use five floorplan benchmarks to test our model. Observing the experimental results, the temperature calculation times for all benchmarks are really direct ratio of total amount of blocks. Hence our block-level thermal model really can reduce the temperature calculating time and provide useful temperature differences for rearranging the floorplan.