ESD protection design on analog pin with very low input capacitance for RF or current-mode applications

Author

Ker, Ming-Dou ; Chen, Tung-Yang ; Wu, Chung-Yu ; Chang, Hun-Hsien

Author_Institution

Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1999

fDate

1999

Firstpage

352

Lastpage

356

Abstract

An ESD design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp devices in the analog ESD protection circuit can be reduced to only 50/0.5 (μm/μm) in a 0.35-μm silicided CMOS process, but it can sustain the HBM (MM) ESD level of up to 6 kV (400 V). With such smaller device dimensions, the input capacitance of this analog ESD protection circuit can be significantly reduced to only ~1.0 pF (including the bond pad capacitance) for high-frequency applications

Keywords

CMOS analogue integrated circuits; UHF integrated circuits; capacitance; current-mode circuits; electrostatic discharge; integrated circuit design; protection; 0.35 mum; 1 pF; 400 V; 6 kV; ESD clamp devices; ESD protection design; RF applications; analog ESD protection circuit; analog I/O pin; bond pad capacitance; current-mode applications; device dimension reduction; efficient power-rails clamp circuit; human body model ESD level; silicided CMOS process; very low input capacitance; Analog integrated circuits; CMOS analog integrated circuits; CMOS technology; Capacitance; Clamps; Electrostatic discharge; MOS devices; Pins; Protection; Radio frequency;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-5632-2

Type

conf

DOI

10.1109/ASIC.1999.806533

Filename

806533