Title :
A frequency modulated PLL for EMI reduction in embedded application
Author :
Michel, J.-Y. ; Neron, C.
Author_Institution :
VLSI Technol., Philips Semicond., Valbonne, France
Abstract :
With the goal of reducing EMI generated by high frequency digital clocks, this paper describes a very flexible way of modulating the output of a standard PLL which provides more than 13 dB of power attenuation at the expense of a small and controlled increase of the clock jitter. The trade-offs are analyzed, and an implementation is presented with measurement results on a test chip
Keywords :
CMOS digital integrated circuits; application specific integrated circuits; clocks; digital phase locked loops; electromagnetic interference; embedded systems; frequency modulation; integrated circuit testing; timing jitter; ASIC design; EMI reduction; VLSI CMOS library; clock jitter; embedded application; frequency modulated PLL; harmonics amplitude; high frequency digital clocks; power attenuation; test chip; triangular wave; Attenuation; Clocks; Digital modulation; Electromagnetic interference; Frequency modulation; Jitter; Phase locked loops; Power generation; Semiconductor device measurement; Testing;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806535
