A 200 MHz, 600 μW CMOS PLL for mobile communication ASICs

Author

Tourette, Bruno

Author_Institution

VLSI Technol., Philips Semicond., Valbonne, France

fYear

1999

fDate

1999

Firstpage

366

Lastpage

369

Abstract

The main design trade-off in the realization of a low power PLL are presented and followed by the description of one implementation. This PLL is designed for mobile communication ASICs, it multiplies frequencies over 8 MHz by a factor of 2 to 8, with a maximum output frequency of 200 MHz. Its power dissipation is less than 600 μW at 200 MHz and 1.8 V. These performances are achieved mainly on the account of the VCO structure choice and the current source design

Keywords

CMOS analogue integrated circuits; application specific integrated circuits; frequency multipliers; integrated circuit design; low-power electronics; mobile communication; phase locked loops; voltage-controlled oscillators; 1.8 V; 200 MHz; 600 muW; CMOS PLL; VCO structure; current source design; design trade-off; frequency multiplication; low power PLL; maximum output frequency; mobile communication ASICs; power dissipation; Application specific integrated circuits; Current supplies; Delay; Frequency; Mobile communication; Phase locked loops; Power dissipation; Ring oscillators; Voltage; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International

Conference_Location

Washington, DC

Print_ISBN

0-7803-5632-2

Type

conf

DOI

10.1109/ASIC.1999.806536

Filename

806536