A low-power Viterbi decoder design for wireless communications applications

Viterbi decoders employed in digital wireless communications are complex and dissipate large amount of power. In this paper, we investigate power dissipation for three different implementations of the Viterbi algorithm for wireless communications applications, including our proposed low-power Viterbi decoder. The schemes employed in our low-power design are clock-gating and toggle filtering. We described the behavior of three Viterbi decoders in VHDL and synthesized using a synthesis tool. The synthesized circuits were placed and routed in the standard cell design environment. Power estimation obtained through gate level simulations indicates that the proposed design reduces the power dissipation of an original Viterbi decoder design by 55%