A low power 25 MS/S 12-bit pipelined analog to digital converter for wireless applications

Author

Aslanzadeh, H.A. ; Mehrmanesh, S. ; Vahidfar, M.B. ; Safarian, A.Q.

Author_Institution

Sharif Univ. of Technol., Iran

fYear

2003

fDate

23-25 Feb. 2003

Firstpage

38

Lastpage

42

Abstract

A 12 bit 25 MS/S pipelined analog-to-digital (A/D) converter was designed and simulated using 0.35 μm CMOS technology. The proposed new high speed class AB opamp makes it possible to achieve requirements of 12 bit resolution and settling in 20 ns within 0.05% accuracy. However, pipeline ADCs are tolerant to comparator´s offset, but using dynamic comparators, power dissipation can be reduced. So a dynamic comparator is designed which is more power efficient. Total power dissipation is about 76 mW from a single 3 V supply, where INL and DNL are 0.8 LSB and 0.6 LSB respectively. A SNDR of 70.1 dB is achieved.

Keywords

CMOS integrated circuits; analogue-digital conversion; circuit simulation; comparators (circuits); integrated circuit design; low-power electronics; network synthesis; operational amplifiers; pipeline processing; 0.35 micron; 12 bit; 20 ns; 3 V; 76 mW; A/D converter; ADC resolution; CMOS technology; DNL; INL; SNDR; high speed class AB opamp; low power analog to digital converter; pipelined ADC; power dissipation reduction; power efficient dynamic comparators; resolution accuracy; settling time; wireless applications; Analog-digital conversion; CMOS technology; Capacitance; Capacitors; Circuit noise; Error correction; Operational amplifiers; Pipelines; Power dissipation; Sampling methods;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2003. Southwest Symposium on

Print_ISBN

0-7803-7778-8

Type

conf

DOI

10.1109/SSMSD.2003.1190393

Filename

1190393