Title :
A reuse oriented design methodology for artificial neural networks implementation
Author :
Titri, S. ; Boumeridja, H. ; Lazib, D. ; Izeboudjen, N.
Author_Institution :
Microelectron. Lab., Dev. Centre of Adv. Technol., Algiers, Algeria
Abstract :
This paper describes a new reuse oriented design methodology for artificial neural networks (ANNs) implementation. The proposed approach is mainly based on a VHDL synthesis environment that uses a pre-designed hierarchical and parametric library suited for different ANN topologies. To validate this approach, a case study of the three-layer back-propagation algorithm is illustrated, A VHDL description of a (5-3-2) ANN circuit is passed through synthesis tool, GALILEO for FPGA implementation. The preliminary results are very successful, since the whole network has been implemented onto only one FPGA. It has a clock frequency of about 16 MHz and can be used in some real time applications
Keywords :
backpropagation; circuit CAD; field programmable gate arrays; hardware description languages; high level synthesis; integrated circuit design; neural chips; ANN implementation; ANN topologies; FPGA implementation; GALILEO; VHDL description; VHDL synthesis environment; artificial neural networks; real time application; reuse oriented design methodology; three-layer backpropagation algorithm; Artificial neural networks; Circuit synthesis; Circuit topology; Clocks; Design methodology; Field programmable gate arrays; Frequency; Libraries; Network synthesis; Network topology;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806544
