Title :
High flexibility CMOS SRAM generator using multiplan architecture
Author :
Clerc, Sylvain ; Dufourt, D. ; Zangara, Louis
Author_Institution :
Retargettable Army Generators Team, Dolphin Integration S.A., Meylan, France
Abstract :
This paper presents a high flexibility CMOS SRAM generator design methodology. The concept of flexibility space is defined and a new merit factor for memory array generators is proposed. A self-timed form factor adaptative controller sequences the memory operations to potentially generate 30000 memory configurations. Critical memory configurations are isolated and simulated to validate the design. A reference memory configuration featuring 2k×16 bits has been fabricated using a 0.35 μm CMOS process. The chip has 1350×1570 μm dimensions and operates at 100 MHz over a 5.5 V to 2.0 V supply range
Keywords :
CMOS memory circuits; SRAM chips; circuit CAD; high level synthesis; integrated circuit design; memory architecture; 0.35 micron; 100 MHz; 2 to 5.5 V; 32 kbit; CMOS SRAM generator; design methodology; flexibility space; high flexibility SRAM generator; macro-cell generator; memory array generators; merit factor; multiplan architecture; reference memory configuration; self-timed form factor adaptative controller; static RAM; Amplitude shift keying; Automatic generation control; Clocks; Decoding; Design methodology; Design optimization; Random access memory; System-on-a-chip; Temperature distribution; Testing;
Conference_Titel :
ASIC/SOC Conference, 1999. Proceedings. Twelfth Annual IEEE International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-5632-2
DOI :
10.1109/ASIC.1999.806546
