A study of nonlinearities for a frequency-locked loop principle [frequency synthesizer application]

Author

Albrecht, Steffen ; Gothenberg, Andreas ; Sumi, Yasuaki ; Tenhunen, Hannu

Author_Institution

Dept. of Microelectron. & Inf. Technol., R. Inst. of Technol., Stockholm, Sweden

fYear

2003

fDate

23-25 Feb. 2003

Firstpage

71

Lastpage

75

Abstract

This paper presents the effect of nonlinearities on data converter resolution. Two models, an exponential and a sinusoidal approach, are proposed to estimate the drop in signal to noise (+distortion) ratio (SNDR). Matlab simulation results predict a loss between 1 dB and 10 dB when introducing a nonlinearity error of up to 2 LSB. These models were used to study the performance loss of a multi-bit converter when used in a frequency synthesizer architecture.

Keywords

circuit simulation; digital-analogue conversion; frequency locked loops; frequency synthesizers; nonlinear network synthesis; voltage-controlled oscillators; 1 dB; 10 dB; DAC; FLL nonlinearities; SNDR loss; VCO; data converter resolution; digital-to-analog converters; exponential model; frequency synthesizer; frequency-locked loop; multibit converter; nonlinearity error; signal to noise/distortion ratio; sinusoidal model; Detectors; Frequency conversion; Frequency locked loops; Frequency synthesizers; Low pass filters; Mathematical model; Phase locked loops; Sampling methods; Voltage control; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2003. Southwest Symposium on

Print_ISBN

0-7803-7778-8

Type

conf

DOI

10.1109/SSMSD.2003.1190399

Filename

1190399