Race-free CMOS pass-gate charge recycling logic (FCPCL) for low power applications

Author

Abbasian, A. ; Rasouli, S.H. ; Derakhshandeh, Jaber ; Afzali-Kusha, Ali ; Nourani, M.

Author_Institution

Electr. & Comput. Eng. Dept., Tehran Univ., Iran

fYear

2003

fDate

23-25 Feb. 2003

Firstpage

87

Lastpage

89

Abstract

A novel logic family called race-free CMOS pass-gate charge recycling logic (FCPCL) has been proposed and analyzed. FCPCL consumes less power with less delay compared to previously reported logic families based on charge recycling. It has the additional benefit of having no sensitivity to signal skew. Using a new regenerator in FCPCL leads to complete elimination of the controller in the circuit, hence the number of transistors was greatly reduced. Considerable improvements in the parameters are proven by simulating a two input NAND gate and a full adder.

Keywords

CMOS logic circuits; adders; circuit simulation; integrated circuit design; logic circuits; logic design; logic simulation; low-power electronics; CMOS logic; FCPCL regenerator; VLSI; charge recycling; circuit controller elimination; full adder; low power logic; race-free pass-gate charge recycling logic; signal skew sensitivity; two input NAND gate; Adders; Application software; CMOS logic circuits; Circuit simulation; Delay; Energy consumption; Laboratories; Logic circuits; Power engineering computing; Recycling;

fLanguage

English

Publisher

ieee

Conference_Titel

Mixed-Signal Design, 2003. Southwest Symposium on

Print_ISBN

0-7803-7778-8

Type

conf

DOI

10.1109/SSMSD.2003.1190402

Filename

1190402