Power and delay estimation of CMOS inverters using fully analytical approach

In this paper, a new simple yet accurate model for determining delay and power consumption of static CMOS inverters is introduced. This analytical model uses the modified version of n-th power law MOSFET model which is appropriate for short channel devices. The short-circuit current, which is used in the calculation of the power consumption, is modeled by a piecewise linear interpolation scheme. For evaluation the delay of the inverter, an accurate model is presented. Although the proposed model is much simpler compared to the previously reported ones, it has a very good accuracy which is confirmed with HSPICE simulations.