Title :
Topological maps for VLSI placement
Author :
Sadananda, R. ; Shrestha, A.
Author_Institution :
Div. of Comput. Sci., Asian Inst. of Technol., Bangkok, Thailand
Abstract :
This paper describes a method of using topological maps in the placement of VLSI cells. A number of algorithms for placement has been reported in view of its importance in the overall VLSI design. The problem in NP-hard. The self-organizing methods shown here can serve as important first draft of the design. The inherent limitation of the serial nature of this method can be overcome by appropriate partition of the input space and also in conjunction with other known methods of VLSI design.
Keywords :
VLSI; integrated circuit layout; network routing; network topology; self-organising feature maps; NP-hard problem; VLSI cell placement; VLSI design; connectivity matrix; input space partition; output neuron 2D array; self-organizing methods; topological maps; Algorithm design and analysis; Computer science; Design methodology; Neural networks; Neurons; Partitioning algorithms; Topology; Very large scale integration;
Conference_Titel :
Neural Networks, 1993. IJCNN '93-Nagoya. Proceedings of 1993 International Joint Conference on
Print_ISBN :
0-7803-1421-2
DOI :
10.1109/IJCNN.1993.717039
