DocumentCode :
3340311
Title :
A novel timing-driven placement using genetic algorithm
Author :
Yoshikawa, Masaya ; Terai, Hidekazu ; Fujita, Tomohiro ; Yamauchi, Hironori
Author_Institution :
VLSI Center, Ritsumeikan Univ., Shiga, Japan
fYear :
2003
fDate :
23-25 Feb. 2003
Firstpage :
237
Lastpage :
242
Abstract :
This paper discusses a novel timing driven placement technique using Genetic Algorithms (GAs), and focuses particularly on the following points: (1) The algorithm has two-level hierarchical structure consisting of outline placement, which partitions a chip area into several areas, and detail placement, which determines cell positions in the partitioned area. The procedure for determining optimal cell positions is then explained. (2) For selection control, which is one of the genetic operations, new multi-objective functions are introduced at each phase for improving delay, reducing congestion and dispersing power. Results show improvement of 14.2% for the worst path delay on average.
Keywords :
CMOS integrated circuits; VLSI; circuit layout CAD; circuit optimisation; delays; genetic algorithms; integrated circuit layout; timing; chip area partitioning; crossover; genetic algorithms; multi-objective functions; mutation; optimal cell positions; outline placement; timing driven placement technique; timing optimization; two-level hierarchical structure; two-level hierarchical vector ranking; wire congestion; Circuits; Delay; Evolution (biology); Genetic algorithms; Intrusion detection; Large scale integration; Partitioning algorithms; Timing; Very large scale integration; Wire;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Mixed-Signal Design, 2003. Southwest Symposium on
Print_ISBN :
0-7803-7778-8
Type :
conf
DOI :
10.1109/SSMSD.2003.1190434
Filename :
1190434
Link To Document :
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