Title :
Accurately modeling speculative instruction fetching in trace-driven simulation
Author :
Bhargava, Ravi ; John, Lizy K. ; Matus, Francisco
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
Abstract :
Performance evaluation of modern, highly speculative, out-of-order microprocessors and the corresponding production of detailed, valid, accurate results have become serious challenges. A popular evaluation methodology is trace-driven simulation which provides the advantage of a highly portable simulator that is independent of the constraints of the trace generation system. While developing and maintaining a trace-driven simulator is relatively easier than other alternatives, a primary drawback is the inability to accurately simulate speculative instruction fetching and subsequent execution. Fetching from an incorrect path occurs often in a speculative processor, however it is difficult to capture this information in a trace. This paper investigates a scheme to accurately model instruction fetching within a trace-driven framework. This is accomplished by recreating an approximate copy of the object code segment, which we call resurrected code, using a preliminary pass through the trace. We discuss a fast and memory-efficient method for implementing this resurrected code
Keywords :
discrete event simulation; instruction sets; microprocessor chips; performance evaluation; Fortran programs; UltraSPARC traces; highly portable simulator; microprocessors; object code segment; performance evaluation; resurrected code; speculative instruction fetching; trace generation system; trace-driven simulation; Character generation; Computational modeling; Computer simulation; Engineering profession; Microprocessors; Monitoring; Out of order; Production; Testing; Timing;
Conference_Titel :
Performance, Computing and Communications Conference, 1999 IEEE International
Conference_Location :
Scottsdale, AZ
Print_ISBN :
0-7803-5258-0
DOI :
10.1109/PCCC.1999.749422