DocumentCode :
3340565
Title :
A test structure for channel length engineering of NAND gates in standard cell library
Author :
Matsuda, T. ; Sugiyama, Y. ; Takakuwa, J. ; Iwata, H. ; Ohzone, T.
Author_Institution :
Dept. of Inf. Syst. Eng., Toyama Prefectural Univ., Toyama
fYear :
2008
fDate :
24-27 March 2008
Firstpage :
76
Lastpage :
79
Abstract :
A channel length engineering technique for optimization of primitive cells in standard cell libraries is proposed and a test structure to analyze the operation performance and leakage current of 3-input NAND is presented. Since the topmost transistor (Nl) in the three series connected n-MOSFETs of 3-input NAND has the largest VDS, subthreshold leakage current can be reduced by optimizing a channel length L of Nl. The leakage current of NANDs for input vector of (0, 1, 1) decreases by about 22 ~ 40 % with the change of L (Nl) from 0.1 to 0.11 mum. The channel length engineering of series connected MOSFETs provides a leakage reduction method for standard cells without significant increase of delay time, maintaining the same cell size.
Keywords :
MOSFET; cellular arrays; logic gates; optimisation; NAND gates; channel length engineering; n-MOSFET; optimization; standard cell library; Delay effects; Leakage current; Libraries; MOSFET circuits; Maintenance engineering; Performance analysis; Subthreshold current; System testing; Threshold voltage; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Microelectronic Test Structures, 2008. ICMTS 2008. IEEE International Conference on
Conference_Location :
Edinburgh
Print_ISBN :
978-1-4244-1800-8
Electronic_ISBN :
978-1-4244-1801-5
Type :
conf
DOI :
10.1109/ICMTS.2008.4509317
Filename :
4509317
Link To Document :
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